Field of Invention
The present invention relates to a chip package and a manufacturing method thereof.
Description of Related Art
Along with the necessary of electronic devices toward lighter and more compact, the semiconductor chip corresponding to the electronic device has a reduced size and increased wiring density. Therefore, it is more difficult and challenging to fabricate a semiconductor chip package in the subsequent process for the semiconductor chip. Wafer-level chip package is a method of packaging the semiconductor chip, which means that all the chips are packaged and tested after completion of manufacturing these chips on the wafer, and then the wafer is cut into single chip packages.
Since the size of the semiconductor chip is decreased and the functional density on the semiconductor chip is increased, the insulating property of the chip is one of the important research directions in the chip packaging techniques to avoid erroneous electrical connection. Generally, an epoxy material has advantages of excellent insulating property, low costs and simple process, so it is widely applied to prepare the isolation layer of the chip package. However, the epoxy material has flowability and is easily affected by the gravity to aggregate, which is not benefit for forming uniform isolation layer, and thus decreases the yield of the chip package.